1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device which has a structure of a memory cell array capable of simultaneously handling many I/O data, and can efficiently execute redundant repair when a failure occurs in a memory cell.
2. Description of the Background Art
In accordance with development of information communications technology in recent years, it has been demanded to provide semiconductor memory devices which have increased memory capacities, and further can perform fast and parallel handling of many data. As a typical example, these features are required in the case when the device is used for data processing of image data.
For satisfying the above demand, semiconductor memory devices having a so-called multi-bank and multi-I/O line structure have been increasingly used. The above structure of the semiconductor memory device has a plurality of banks each allowing independent reading and writing, and is provided with a large number of parallel I/O lines for allowing simultaneous handling of large volumes of data.
In the semiconductor memory device having a large-scaled memory cell array, it is important to employ an appropriate redundant repair technique for ensuring intended yields of products. According to the redundant repair technique, a defect in memory cells which occurred during manufacturing is repaired by a spare memory cell in a redundant circuit which is already prepared on the same chip.
With increase in memory capacity, it is desired or required to perform the redundant repair efficiently. For example, Japanese Patent Laying-Open No. 8-8344 has disclosed a technique of shift redundancy, in which redundant repair is performed a data line at a time by successively shifting the connections between the data lines. This prior technique will be referred to as a "prior art 1" hereinafter.
In addition, Japanese Patent Laying-Open No. 8-77793 has disclosed a technique, which will be referred to as a "prior art 2" hereinafter. In this prior art 2, a plurality of memory cell arrays (corresponding to banks), each of which allows read/write of data independently of the other memory cell arrays, commonly use a redundant circuit so that an efficient layout design can be performed.
However, the foregoing prior arts 1 and 2 would cause a problem if they were applied to the semiconductor memory device having the foregoing multi-bank and multi-I/O line structure without modification or change.
In the prior art 1, replacement of memory cells with spare cells is not performed a row at a time or a column at a time, but is performed by shifting the form of connection, which is made between data lines in the position including the defective memory cell. However, the setting for shifting the connection between data lines is designated in a fixed manner based on address program information, which is stored in advance in fuse elements or the like. Accordingly, if this prior art is applied to the multi-bank structure, the enormous number of fuse elements are required. The fuse element has a relatively large area, and therefore is not suitable to high-density integration. Thus, the fuse elements significantly affect the layout design.
According to the prior art 2, the units (banks) in the memory cell array, each of which can perform the read/write operations independently of the others, commonly use the same redundant circuit. According to this structure, it is necessary for input/output of data to provide switch circuits which can transmit data between respective data I/O lines and the redundant circuit. In the multi-bank and multi-I/O line structure, the required switch circuits are extremely large in number, and therefore the redundant repair circuit requires an extremely large area.